On semiconductor wafer products, and especially on SOI (silicon on insulator) wafer products, defects, in particular voids, can occur in the vicinity of the outer periphery of the compound-material wafer. The outer periphery of wafers with such defects can not be readily used for subsequent semiconductor device fabrication.
One known method for reducing the number of such defects of this type includes carrying out the SOI fabrication process with wafers for which the configuration change is 0.1 nm (nanometer) or less, in a region between 10 mm (millimeter) and 3 mm away from the outer periphery. See, e.g., EP 1566830 (also U.S. publication no. 2006/0024915A1 published Feb. 2, 2006). Alternatively, wafers with a slope of 0.02% or less at a position of 5 mm away from the outer periphery lead to SOI wafers with reduced defects.
Other methods for reducing the number of such defects, and thereby permitting more complete utilization of compound-material wafers, would be advantageous.